Wrapped Channel FET (WCFET): Future of Low Power Application

Wrapped Channel FET (WCFET): Future of Low Power Application

Iqbal Hasan, Pranav Kumar Asthana, Yogesh Goswami, S. A. M. Rizvi
DOI: 10.4018/IJECME.297084
OnDemand:
(Individual Articles)
Available
$37.50
No Current Special Offers
TOTAL SAVINGS: $37.50

Abstract

In this article, we examined the electrical characteristic of proposed new device structure, Wrapped Channel Field Effect Transistor (WCFET). Results of WCFET have been analyzed using Atlas 3-D simulator. WCFET shows better transfer characteristics with ON-current ION of ~10-6A and leakage current IOFF of ~10-16 A. Optimization of device characteristics has done with doping concentration (ND), gate work function (ΦG) and spacer dielectric. Impact of gate length and semiconductor film thickness variation on drain current, subthreshold slope (SS) and DIBL are also investigated. Further, effects of various gate dielectric materials such as SiO2, Si3N3, HfO2 and TiO2 are examined w.r.t. switching characteristics of WCFET. To validate of device compatibility with power supply scaling, we inspected full range variation of VDS ≈ (0.05V-to-0.7V) on transfer characteristics.
Article Preview
Top

1. Introduction

To meet the demand of semiconductor market, the density of transistors in a chip is increasing rapidly. The formation of ultra sharp and shallow source/drain, PN junction in multigate devices is challenging task for semiconductor technologists. So researchers started searching for alternative solution of these bottlenecks. Gate -all-around junction less FET(GAA-JLFET) is one of the most promising candidates for future CMOS technology due to their improved electrostatic control compared to double gate as well as bulk devices Morita (2013), Suzuki (1993), Frank (1998), Hu (1993), Li (2009), Ray (2008). However, it is limited by the scalability as fabrication procedure requires very high level of calibration and precision. Further, randomness added for less than 20nm process makes it unviable. Junctionless field-effect transistor is under evaluation as potential replacements for traditional planner transistors in upcoming sub-20 nm technology nodes. It is potential solution to random dopant fluctuation as it contains uniformly doped channel. Additionally, it has suppressed short channel effects and high switching speed Suzuki (1993). However, low improvement in sub threshold slope makes junctionless transistors power hungry devices and hinders junctionless FET (JLFET) from potential applications. There have been multiple attempts to optimize the power and performance trade-off using various approaches however, there’s still scope of improvement [8-16]. This bottleneck can be solved using WCFET which highly suppresses leakage current. In this work, we have proposed a novel device structure, Wrapped Channel Field Effect Transistor (WCFET). The proposed device has several advantages such as better gate control, low leakage current (IOFF) and easy fabrication process than junction-based devices such as double gate conventional MOSFETs, FINFET etc. WCFETs can be seen as seen as amalgamation of FINFETs and SOI structures, bringing advantages of both the models.

Complete Article List

Search this Journal:
Reset
Volume 12: 1 Issue (2024): Forthcoming, Available for Pre-Order
Volume 11: 2 Issues (2022): 1 Released, 1 Forthcoming
Volume 10: 2 Issues (2021)
Volume 9: 2 Issues (2020)
Volume 8: 2 Issues (2019)
View Complete Journal Contents Listing