Design and Performance Analysis of High Throughput and Low Power RNS-Based FIR Filter Design on FPGA

Literature Survey

Before this, efficient multipliers of a different type had been built. Chen et al. (2003) presented a low power consumption multiplication by minimizing partial product switching movements using the application Booth technique and presented a low-power 2's complement multiplier. The Radix-4 Booth method is used to reduce the number of Partial Product switching activities. Wang et al. (2004) suggested a multiplier with fixed-width using the left-right technique. One of the downsides of this fixed-width multiplier is that the power dissipation is relatively high in comparison to the cost, while one of the benefits is that it minimizes Partial Product to improve multiplication performance. Huang and Ercegovac (2005) describe a linear array multiplier structure that is built by combining several methodologies. The disadvantage of this design is that it requires substantially more time and space, but it is also more energy-efficient. Chen and Chu (2007) used spurious power suppression to the compaction tree of the multiplier and the Booth decoder, resulting in multiplier architecture with significantly lower power and a very fast speed of operation. The recommended design's area consumption is higher, and this is one of its disadvantages regrettably. Two 32-bit multipliers proposed by Krad and Al-Taie (2008) are examined using a ripple carry adder and a carry-look-ahead adder for the combination of Partial Products. Dastjerdi and others proposed the shift-add multipliers BZ-FAD (Mottaghi-Dastjerdi et al., 2009) decrease power consumption by minimizing opportunities to evolve. Saha et al. (2013) proposed an 8-bit multiplier with fast speed and low power consumption that is based on a pair-wise method. The overall efficiency of the proposed model is high due to the use of wave pipelining regrettably. Liu et al. (2014) have proposed an approximate repeater with a short right trajectory and high power efficiency for error-tolerant purposes. Mohanty and Tiwari (2014) proposed a radix-4 Booth multiplier with improved probabilistic estimate bias (PEB) for uses such as digital signal processing. It has also been recommended that a probabilistic estimate bias multiplier be used for an adequate adder. Shao and Li (2015) suggested a squarer and a 16-bit Booth multiplier with a fixed width that has optimal area and energy. To handle the squarer and multiplier structure (AAAC) unique array architecture, based on approximate arithmetic computing, has been provided. He et al. (2016) describes a Booth multiplier with a fixed width and high speed that is based on the conditional probability of input series. A few of the benefits of this multiplier is that it reduces computing costs while increasing velocity. Shabbir et al. (2016) used the Dadda algorithm to create a multiplier with high speed and low power consumption. Full adders are advised for the use of boosters. Defects in the outcome are reduced by using flip-flops in converters.