Mário Pereira Véstias

Mário Pereira VéstiasMário Véstias received the PhD in electrical and computer engineering in 2002, both from the Technical University of Lisbon, Portugal. He is a Coordinate Professor at the Polytechnic Institute of Lisbon, School of Engineering (ISEL), Department of Electronic, Telecommunications and Computer Engineering (DEETC), where he is responsible for undergraduate and graduate courses on computer architecture and digital systems design. He is also a senior researcher at the ESDA (Electronic Systems Design and Automation) group at the research institute INESC-ID in Lisbon. His main current research interests are Computer Architectures and Digital Systems for Embedded Reconfigurable Computing.

Publications

Convolutional Neural Network
Convolutional Neural Network
Mário Pereira Véstias. © 2022. 17 pages.
Machine learning is the study of algorithms and models for computing systems to do tasks based on pattern identification and inference. When it is difficult or infeasible to...
Deep Learning on Edge: Challenges and Trends
Deep Learning on Edge: Challenges and Trends
Mário P. Véstias. © 2022. 21 pages.
Deep learning on edge has been attracting the attention of researchers and companies looking to provide solutions for the deployment of machine learning computing at the edge. A...
Convolutional Neural Network
Convolutional Neural Network
Mário Pereira Véstias. © 2021. 15 pages.
Machine learning is the study of algorithms and models for computing systems to do tasks based on pattern identification and inference. When it is difficult or infeasible to...
High-Speed Viterbi Decoder
High-Speed Viterbi Decoder
Mário Pereira Véstias. © 2021. 12 pages.
The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. Trellis decoding is used to recover encoded information that was corrupted...
Field-Programmable Gate Array
Field-Programmable Gate Array
Mário Pereira Véstias. © 2021. 14 pages.
Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be...
Deep Learning on Edge: Challenges and Trends
Deep Learning on Edge: Challenges and Trends
Mário P. Véstias. © 2020. 20 pages.
Deep learning on edge has been attracting the attention of researchers and companies looking to provide solutions for the deployment of machine learning computing at the edge. A...
Adaptive Networks for On-Chip Communication
Adaptive Networks for On-Chip Communication
Mário Pereira Vestias. © 2019. 12 pages.
The second generation of network-on-chips (NoC) are dynamic or adaptive providing a new set of benefits in terms of area overhead, performance, power consumption, fault...
Decimal Hardware Multiplier
Decimal Hardware Multiplier
Mário Pereira Vestias. © 2019. 15 pages.
IEEE-754 2008 has extended the standard with decimal floating-point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the...
High-Performance Reconfigurable Computing
High-Performance Reconfigurable Computing
Mário Pereira Vestias. © 2019. 14 pages.
High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable...
Viterbi Decoder in Hardware
Viterbi Decoder in Hardware
Mário Pereira Véstias. © 2019. 15 pages.
Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well-known trellis-based...
High-Performance Reconfigurable Computing
High-Performance Reconfigurable Computing
Mário Pereira Vestias. © 2018. 12 pages.
High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable...
Adaptive Networks for On-Chip Communication
Adaptive Networks for On-Chip Communication
Mário Pereira Vestias. © 2018. 11 pages.
The second generation of Network-on-Chips (NoC) are dynamic or adaptive providing a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance...
Decimal Hardware Multiplier
Decimal Hardware Multiplier
Mário Pereira Vestias. © 2018. 12 pages.
IEEE-754 2008 has extended the standard with decimal floating point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the...
Viterbi Decoder in Hardware
Viterbi Decoder in Hardware
Mário Pereira Véstias. © 2018. 12 pages.
Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well known trellis-based...