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Top1. Introduction
Analog circuit design and sizing is a very complicated and iterative process. Unlike its digital counterpart, it has not yet reached a mature stage. This is due to many reasons, mainly because the analog design field presents an extra large spectrum of circuit performances, constraints and tradeoffs. Designers generally count on their experience and on the use of iterative simulations to optimize their circuits. Therefore, there is a pressing need for analog circuit design automation (Gielen & Rutenbar, 2000). Recent advances in design automation have led to a gradual transition from the hand-calculation based design, namely knowledge-based design, to the optimization-based design. Knowledge-based approaches are characterized by the use of a predefined design plan describing how the circuit components must be sized to reach the optimum solution of the design problem (Shravan et al., 2011; Degrauwe et al., 1987; Harjani et al., 1989; El-Turky & Perry, 1989). On the other hand, the optimization-based approaches use an iterative search algorithm for solving the circuit’s sizing problem.
Actually, two different techniques can be adopted for solving such problem:
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The equation-based optimization technique, which uses symbolic (or semi-symbolic) expressions of both performances and constraints to evaluate the circuit’s performance(s) and to generate the optimal values of the circuit’s parameters. These equations can be derived manually (for small size problems), or by using a symbolic analyzer (for medium and large size problems), such as, OPASYN (Koh et al., 1990), STAIC (Harvey et al., 1992), CASCADES (Fakhfakh & Loulou, 2010). The advantage of this approach, i.e., the equation-based technique, mainly consists of the reduced computation time, since the evaluation of the performance is performed by direct evaluation of symbolic equations. However, generally such equations are marred by errors. These errors are due to the unavoidable use of simplified models of non-linear components, mainly transistors’ models.
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The simulation-based technique evaluates the circuit’s performances, as well as its constraints, using a circuit simulator, such as SPICE. Thus, one directly takes benefits of the simulator models without any need of simplifications. In other words, the final result corresponds exactly to the expected one (Guerra-Gomez et al., 2008, 2010)
In this paper we present in details ‘‘SODAC’’; a simulation-based optimization tool, and we highlight via some examples the advantages and the necessity of the use of such sizing/optimization tool. Comparisons with other approaches are given, and simulation results are presented to further highlight these statements.
The rest of the paper is structured as follows. In Section 2, we put the light on the proposed tool and highlight its capabilities. In Section 3, we present some application examples where we show the usefulness of such tool: First, we deal with optimizing performances of analog circuits, namely current conveyors. Second, we focus on the use of current conveyors as building blocs for the design of active circuits. In Section 4, we present details of the multi-objective module of SODAC and we show case its viability via two examples. Finally, concluding remarks are given in Section 5.
Top2. The Simulation-Based Sizing/Optimization Technique
One of the key components in the simulation based optimization technique is the optimization bloc. The purpose of this optimizer is to find a set of parameters that optimizes the (set of) performance function(s) while satisfying a set of constraints (see expression (1)).Minimize 
Subject to:and:
(1) where
k,
m,
n and
l denote numbers of objectives, inequality constraints, equality constraints and parameters, respectively.